Fabrication of integrated devices, for example, and without limitation, semiconductor integrated devices, is complicated and, due to increasingly stringent requirements on device designs due to demands for greater device speed, fabrication is becoming ever more complicated. For example, integrated circuit geometries have decreased in size substantially since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed a two year/half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years. Today's fabrication facilities are routinely producing devices having 0.13 μm feature sizes, and tomorrow's facilities soon will be producing devices having even smaller feature sizes. In addition, integrated circuits are being layered or stacked with ever decreasing insulating thickness between each circuitry layer.
In the production of advanced integrated circuits that have minimum feature sizes of 0.13 μm and below, problems of RC delay, power consumption, and crosstalk become significant. For example, device speed is limited in part by the RC delay which is determined by the resistance of metals used in the interconnect scheme, and the dielectric constant of insulating dielectric material used between metal interconnects. In addition, with decreasing geometries and device sizes, the semiconductor industry has sought to avoid parasitic capacitance and crosstalk noise caused by inadequate insulating layers in the integrated circuits. One way to achieve the desired low RC delay and higher performance in integrated circuit devices involves the use of dielectric materials in the insulating layers that have a low dielectric constant (k).
As the required value for the dielectric constant of materials is decreased due to device performance demands, there are many different types of low-k materials that are being investigated to determine whether they can perform acceptably. Most of these candidates are porous materials that can be organic materials, inorganic materials, organic compositions that might include inorganic components, and so forth. Further, ongoing investigations are exploring electron beam treatment of such films to improve their properties and/or to lower their dielectric constant. For example, such electron beam treatment can lower the dielectric constant and improve mechanical properties.
As used herein, the term electron beam or e-beam treatment refers to exposure of a film to a beam of electrons, for example, and without limitation, a relatively uniform beam of electrons. The e-beam may be scanned across a wafer, or the e-beam may be sufficiently broad to encompass a substantial portion, or the entirety, of a wafer (to achieve higher throughput processing it is advantageous to use a large-area or flood beam electron source, to expose the whole substrate simultaneously). The energy of the e-beam during the exposure is such that substantially an entire thickness of a layer of material is exposed to electrons from the e-beam, or predetermined portions of the layer beneath the surface of the layer are exposed to electrons from the e-beam. The exposure may also be accomplished in steps of varying energy to enable the whole layer, or portions of the layer to be exposed at predetermined depths.
In general, it is desired to have a method for characterizing such an electron beam treatment apparatus, i.e., a method for determining one or more measures that might provide insight into its performance. Such a method of characterizing might be carried out before utilizing such an electron beam treatment apparatus in production to provide qualification assurance, and it might be carried out after the apparatus has been in production for some time to determine whether maintenance and/or repair is required. One such measure used today is a measure of electron beam uniformity. Typically, a method of determining electron beam uniformity entails measuring film shrinkage (related to film thickness) after electron beam treatment of coated wafers, and this entails studying shrinkage maps whose results may depend on electron beam energy, electron beam dose amounts, and/or wafer temperature. This is problematic because, among other things, the process of studying shrinkage maps consumes much time. As a result, this does not provide a practical method for determining a measure of electron beam uniformity.
In light of the above, there is a need to overcome one or more of the above-identified problems.